[IA64] Fix RSE issue in VTI-domain

Signed-off-by: Anthony Xu <anthony.xu@intel.com>

diff --git a/xen/arch/ia64/vmx/vmx_entry.S b/xen/arch/ia64/vmx/vmx_entry.S
index 7e35fa13ea55e93d7de64a2d8a7d14032358f481..c0d4aa8861210d6c51819fad039df427d422d7ba 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_entry.S
+++ b/xen/arch/ia64/vmx/vmx_entry.S
@@ -315,7 +315,9 @@ vmx_dorfirfi_back:
     adds r18=IA64_VPD_BASE_OFFSET,r21
     ;;
     ld8 r18=[r18]   //vpd
+    adds r17=IA64_VCPU_ISR_OFFSET,r21
     ;;
+    ld8 r17=[r17]
     adds r19=VPD(VPSR),r18
     ;;
     ld8 r19=[r19]        //vpsr
@@ -337,6 +339,7 @@ GLOBAL_ENTRY(ia64_vmm_entry)
 /*
  *  must be at bank 0
  *  parameter:
+ *  r17:cr.isr
  *  r18:vpd
  *  r19:vpsr
  *  r20:__vsa_base
@@ -348,8 +351,14 @@ GLOBAL_ENTRY(ia64_vmm_entry)
     tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT        // p1=vpsr.ic
     ;;
     (p1) add r29=PAL_VPS_RESUME_NORMAL,r20
+    (p1) br.sptk.many ia64_vmm_entry_out
+    ;;
+    tbit.nz p1,p2 = r17,IA64_ISR_IR_BIT                //p1=cr.isr.ir
+    ;;
+    (p1) add r29=PAL_VPS_RESUME_NORMAL,r20
     (p2) add r29=PAL_VPS_RESUME_HANDLER,r20
     ;;
+ia64_vmm_entry_out:    
     mov pr=r23,-2
     mov b0=r29
     ;;

diff --git a/xen/arch/ia64/vmx/vmx_interrupt.c b/xen/arch/ia64/vmx/vmx_interrupt.c
index 2526ca4b75bc034f65787b0de7555fb701212798..abf2313496138bc0b052ff7d7095d2ee0257f5a3 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_interrupt.c
+++ b/xen/arch/ia64/vmx/vmx_interrupt.c
@@ -91,8 +91,12 @@ inject_guest_interruption(VCPU *vcpu, u64 vec)
 {
     u64 viva;
     REGS *regs;
+    ISR pt_isr;
     regs=vcpu_regs(vcpu);
-
+    // clear cr.isr.ri 
+    pt_isr.val = VMX(vcpu,cr_isr);
+    pt_isr.ir = 0;
+    VMX(vcpu,cr_isr) = pt_isr.val;
     collect_interruption(vcpu);
 
     vmx_vcpu_get_iva(vcpu,&viva);

diff --git a/xen/arch/ia64/vmx/vmx_ivt.S b/xen/arch/ia64/vmx/vmx_ivt.S
index 81b3e646369af115bfa78761ed12333277739572..7e54c84862008ff85afc641a3e825a17346120e0 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_ivt.S
+++ b/xen/arch/ia64/vmx/vmx_ivt.S
@@ -172,6 +172,7 @@ vmx_itlb_loop:
     ;;
     srlz.i
     ;;
+    mov r17=cr.isr
     mov r23=r31
     mov r22=b0
     adds r16=IA64_VPD_BASE_OFFSET,r21
@@ -237,6 +238,7 @@ vmx_dtlb_loop:
     ;;
     srlz.d;
     ;;
+    mov r17=cr.isr
     mov r23=r31
     mov r22=b0
     adds r16=IA64_VPD_BASE_OFFSET,r21